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W53300/W53320
16" Voice/Melody/LCD Controller (ViewTalkTM Series)
GENERAL DESCRIPTION FEATURES BLOCK DIAGRAM PIN DESCRIPTION FUNCTIONAL DESCRIPTION
PART A: UC FUNCTION Program Counter (PC) Stack Register (STACK) Program Memory (ROM) 1. Architecture 2. Look-Up Table Pointer Register(LUP3, LUP2, LUP1, LUP0 and LUC) Data Memory (RAM) 1. Architecture 2. Working Register Page (WRPAGE with SR=30H) 3. RAM Point Register (RP0L, RP0M, RP0H, RP1L, RP1M, RP1L) Special Register and Special Register Pair (SR & SRP) Accumulator (ACC) Arithmetic and Logic Unit (ALU) Carry Flag Register (CF with SR=20H) Clock Generator Dual-clock operation System Control Register (SCR with SR=2BH) Divider Watchdog Timer (WDT) FLAG1 Register (FLAG1 with SR=23H) Timer/Counter 1. Timer 0 (TM0) 2. Timer 1 (TM1) Mode Register 0 (MR0 with SR=28H) Mode 1 Register (MR1 with SR=29H) Interrupts Mode Register 2 Register (MR2 with SR=26H) Interrupt Enable Flag Register (IEF with SRP=07H) Hold Mode Operation Event Flag Register (EVFL, EVFH with SR=0AH & 0BH)
3 3 5 6 7
8 8 8 8 8 9 10 10 10 11 12 14 14 14 14 15 16 16 16 16 18 18 18 20 20 20 21 21 23 23
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Publication Release Date: March 1999 Revision A2
W53300/W53320
Hold Mode Release Enable Flag Register (HEF with SRP=06H) Hold Mode Release Condition Flag Register (HCFL, HCFH with SR=10H & 11H ) Input/Output Ports RA, RB Port Mode 0 Register (PM0 with SR=32H) Port Mode Register 1 and 2 (PM1, PM2 with SR=36H, 37H) Port A Register (PORTA with SR=38H) Port B Register (PORTB with SR=39H) Input Ports RC, RD Port Enable Flag for hold mode (PEFL, PEFH with SR=14H, 15H) Port Status Register 0 and 1 (PSR0, PSR1 with 34H, 35H) Port C Register (PORTC with SR=3AH) Port D Register (PORTD with SR=3BH) Output Port RE Port E Register (PORTE with SR=3CH) Reset Function PART B: SPEECH and MELODY FUNCTION Mode Register 3 ( MR3 with SR=27H ) FLAG0 Register (FLAG0 with SR=22H) SPEECH Function Speech Section Register (SPCL, SPCH with SR=1EH & 1FH) Melody Function Melody Scores Register (MLDL, MLDH with SR=1CH, 1DH) PART III: LCD FUNCTION LCD Pattern RAM (LCDR000H~LCDR17FH) LCD Mode Register 1 (LCDM1 with SR=2AH) LCD Example and Waveform: 24 25 25 25 26 27 27 28 28 28 29 29 30 30 31 32 32 32 33 34 34 35 36 36 38 40
TYPICAL APPLICATION CIRCUIT INSTRUCTION SET SUMMARY
43 44
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W53300/W53320
GENERAL DESCRIPTION
The W53300/W53320 is a high-performance 4-bit microcontroller (C) with built-in speech, melody and 32*48 LCD driver which includes internal pump circuit. The 4-bit uc core contains dual clock source, 4-bit ALU, two 8-bit timers, one divider, 20 pin input or output, 7 interrupt sources and 8-level subroutine nesting for interrupt applications. Speech unit can be implemented with Winbond 16-sec Power Speech using ADPCM algorithm. Melody unit provides dual tone output and can store up to 1k notes. Power reduction mode is also built in to minimize power dissipation. It is ideal for games, educational toys, remote controllers, watches, clocks and other application products which incorporate both LCD display and melody.
FEATURES
* Operating voltage: 2.4~5.5Volt * Dual clock operating system
- RC/Crystal (400 KHz to 4 MHz) for main clock - 32.768 KHz crystal oscillation circuit for sub-oscillator
* Memory
- 16k x 20 bit program ROM - 512 x 4 bit (W53320) / 704 x 4 bit (W53300) general data RAM - 384 x 4 bit (W53320) / 192 x 4 bit (W53300) LCD data RAM
* 20 input/output pins
- Ports for input only: 2 ports/8 pins - Input/output ports: 2 ports/8 pins - Port for output only: 1 port /4 pins
* Power-down mode
- Hold function: no operation (except for oscillator)
* Seven types of interrupts
- Five internal interrupts (Divider ,Timer 0, Timer 1, Speech, Melody) - Two external interrupts (Port RC, Port RD)
* One built-in 14-bit clock frequency divider circuit * Two built-in 8-bit programmable countdown timers
- Timer 0: one of two internal clock frequencies (FOSC/4 or FOSC/1024) can be selected - Timer 1: built-in auto-reload function includes internal timer, external event counter from RC.0 or TONE output function (can be used as IR carrier output if main clock is 455kHz) * Built-in 18/14-bit watchdog timer for system reset by mask code option * Over 500 powerful instruction sets * 8-level subroutine (including interrupt) nesting
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Publication Release Date: March 1999 Revision A2
W53300/W53320
* LCD driver output
- 32 common x 48 segment (W53320), 16 common x 48 segment (W53300) - 1/16 or 1/32 duty, 1/5 or 1/7 bias, internal pump circuit option by special register
* Speech function
- Provides 384 kbits dedicated speech ROM - Direct driving output for speaker - Maximum 256 sections available * Melody function - Provides 22 kbits dedicated melody ROM -Provides 6 kinds of beat, 16 kinds of tempo, and pitch range from G3# to C7 -Tremolo, triple frequency and 3 kinds of percussion available - Direct driving output for speaker - Maximum 32 scores available * Mix speech with melody available * Multi-engine controller * PWM output current option * Chip On Board available
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W53300/W53320
BLOCK DIAGRAM
SEG0 to SEG47 COM0 to COM31 V2 ~ V6 VDD2 VDD3 DH1, DH2
RAM (896*4)
LCD DRIVER
VLCD PUMP CIRCUIT
VDD TEST
PORT RA ROM (16K*20) ALU PORT RB ACC
RA0~3
RB0~3
PORT RD PC Special Register
IEF HCF HEF EVF PM0 RP0L PEF FLAG1 MR1 LUP2 RP0M MLDH FLAG0 SPCH LUP3 RP0H TONE SPC_busy
RD0~3
PORT RC
RC0~ 3
STACK (8 Levels)
PSR0 LUC
PORT RE
RE0 to 3 LED1 LED2 ROSC PWM1 PWM2
LUP0 LUP1
.
.
.
.
SPC_busy
Speech (384Kbit ROM)
Timer 0 (8 Bit)
Timer 1 (8 Bit)
Interrup & Hold Mode Release
MLD_busy MLD_play
Dual Tone Melody (1K*22 ROM)
Watch Dog Timer (18/14 Bit)
Divider (14/10 Bit)
Timing Generator
VDDP VSS RES
XIN
XOUT
X32I
X32O
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Publication Release Date: March 1999 Revision A2
W53300/W53320
PIN DESCRIPTION
SYMBOL XIN I/O I FUNCTION Input pin for oscillator. It can be connected to crystal, or can connect a resistor to VDD to generate main system clock. Oscillator can be stopped when SCR.1 is set to logic 1. Output pin for oscillator which is connected to another crystal pin. 32.768 KHz crystal input pin. 32.768 KHz crystal output pin. General Input/Output port specified by PM1 register. If output mode is selected, PM0 register can be used to specify CMOS/NMOS driving capability option. Initial state is input mode. General Input/Output port specified by PM2 register. If output mode is selected, PM0 register can be used to specify CMOS/NMOS driving capability option. Initial state is input mode. 4-bit schmitt input port with internal pull high option specified by PM0 register. RC0 can be used as clock source for Timer 1. Each pin has an independent interrupt capability specified by PEFL special register. 4-bit schmitt input port with internal pull high option specified by PM0 register. Each pin has an independent interrupt capability specified by PEFH special register. Output port only. RE3 may use as TONE if bit 0 of MR0 special register is set to logic 1. System reset pin with internal pull-high resistor is active low. Test pin. Connected to low for normal use. Connects resistor to VDD to generate speech or melody clock source. Power source for PWM output. Synchronous LED1 output while speech play/melody is active. Synchronous LED2 output only while speech play is active. Speaker direct driving output 1 while speech or melody is active. Speaker direct driving output 2 while speech or melody is active. LCD segment output pins. LCD common signal output pins. The LCD alternating frequency is fixed at 64Hz. Connection terminals for voltage doubler capacitor. Connects a 1uF capacitor to VSS to double VDD voltage output if triple pump option is enabled. Otherwise, VDD2 connects to VDD directly if double pump option is enabled.
XOUT X32I X32O RA0 ~ RA3
O I O I/O
RB0 ~ RB3
I/O
RC0 ~ RC3
I
RD0 ~ RD3
I
RE0~ RE3/TONE
RES
O I I I I O O O O O O I O
TEST ROSC VDDP LED1 LED2 PWM1 PWM2 SEG0-SEG47 COM0-COM31 DH1, DH2 VDD2
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W53300/W53320
VDD3
O/I
An output if internal pump circuit is enabled. It connects a 1uF capacitor to VSS. Triple VDD voltage will be output if triple pump option is enabled. Otherwise, double VDD voltage will be output if double pump option is enabled. An input if internal pump voltage is disabled. LCD COM/SEG output driving voltage. If internal shunt resistor is disabled, external resistors need to be supplied to V2, V3, V4, V5. A capacitor is suggestted for stable LCD voltage level. External variable resistor connects between VDD3 and V6 to adjust maximun LCD output voltage level. Microcontroller Positive power supply (+). Negative power supply (-). Negative power supply (-).
V2 ~ V5
O
V6 VDD VSS1 VSS2
I I I I
FUNCTIONAL DESCRIPTION
There are four main units in W53300/W53320 : 4 bit uC, Power Speech, dual-tone melody and 16com/32 com * 48 seg LCD driver. The 4 bit uC is modified from Winbond W741C260 with many features enhanced, such as larger ROM and RAM space, addressing capability, more instruction sets, 7 interrupt sources, speech control, capability for playing melody directly to drive speaker, and so on. The following sections, Parts A, B, and C will explain the functions in detail.
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Publication Release Date: March 1999 Revision A2
W53300/W53320
PART A: UC FUNCTION
Program Counter (PC) Organized as a 14-bit binary counter (PC0 to PC13), the program counter generates the addresses of the 16K x20 on-chip ROM containing the program instructions. When jump instructions, subroutine calls, interrupts, or initial reset conditions are executed, the address corresponding to the next instruction will be loaded into the program counter. Table 1 lists the formats used. ITEM Initial Reset INT 0 (DIV) INT 1 (TM 0) INT 2 (RC) INT 3 (RD) INT 4 (Reserved) INT 5 (SPEECH) INT 6 (MELODY) INT 7 (TM 1) JP Instruction Subroutine Call ADDRESS 0000H 0004H 0008H 000CH 0010H 0018H 001CH 0020H XXXXH XXXXH INTERRUPT PRIORITY 1st 2nd 3rd 4th 5th 6th 7th -
Table 1: Interrup Address Assignment & Priority
Stack Register (STACK) The stack register is organized as 14bits x 8 levels (first-in, last-out). When a subroutine call or an interrupt is executed, the program counter will be pushed onto the stack register automatically. At the end of a subroutine call or an interrupt service subroutine, the RTN instruction must be executed to pop the content of the stack register into the program counter. When the stack register is pushed over the eighth level, the content of the first level will be lost. In other words, a maximum of 8 subroutine nestings are allowed in the stack register. Program Memory (ROM) 1. Architecture The read-only memory (ROM) of size 16K x20 bit is used to store program codes addressing PC from 0000H to 3FFFH. Locations 0000H through 0020H are reserved for interrupt service as shown in Figure 1. All instruction sets are one word, one cycle. Look-up table function is provided to access ROM code of all 16k ROM spaces. The program memory map is shown in Figure 1.
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W53300/W53320
20 bits 0000H 0004H 0008H 000CH 0010H 16384 0014H address 0018H 001CH 0020H : Reset start DIV TM 0 RC RD reserved SPEECH MELODY TM 1 This area can be used to store both instruction code and look table data and look-up table.
:
3FFFH
16K * 20 bits
Figure 1. Program Memory Map 2. Look-Up Table Pointer Register(LUP3, LUP2, LUP1, LUP0 and LUC) The LUPC (Look-up table address Pointer Counter) is used to access data in the 16K ROM space. It includes 5 consecutive registers, LUP3 (Look-Up table Pointer), LUP2, LUP1, LUP0, and LUC (LookUp table data Counter). LUP3, LUP2, LUP1 and LUP0 together store the 14-bit ROM address for accessing data in the 16k-word ROM, and every single 20-bit ROM word is separated into 5 nibbles. As described in the following equation, LUPC = LUPC.13~LUPC.0 + LUC.3~LUC.0 LUPC.13~LUPC.0 mapping from 0000H to 3FFFH is used as word address of 16K ROM. LUC is used to determine which nibble of the word data is accessed, and counts from 0 to 4 cyclically. The instruction MOV LUPn, ACC can write initial address pointer of look-up table into LUPC, and resets LUC register to 0. LUPC is increased by 1 when LUC is increased by 1, and LUP0 is increased by 1 when LUC counts from 4 to 0. LUP1 is increased by 1 when LUP0 is counted from 0xF to 0. LUP3 and LUP2 follow the same rule as LUP1. The LUC will be increased by 1 automatically when symbol @LUPC++ is used. Registers LUP3~LUP0 can be read/write by user, but LUC register is read only. At initial reset, all registers are initialized to 0000B.
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Publication Release Date: March 1999 Revision A2
W53300/W53320
3 X 2 X 3 2 1 0 0 LUP.13 LUP.12 LUP.11 LUP.10 LUP.9 LUP.8 LUP2 1 0 LUP.4 3 2 1 0 1
LUP3 3 2
LUP.7 LUP.6 LUP.5 LUP1 2
LUP.3 LUP.2 LUP.1 LUP.0 LUP0
3
1
0
LUC.3 LUC.2 LUC.1 LUC.0 LUC Data Memory (RAM) 1. Architecture The static data memory (RAM) is arranged as (512+384) x 4 bits. Data memory can be addressed directly or indirectly. The mapping of the data memory, using W53320 as example, is shown in Figure 2. The first 512 nibbles RAM mapping from 000H to 1FFH are allocated for general data memory. Data memory from 200H to 37FH can be allocated as an LCD dedicated pattern data memory as mapping in Table 5, or as a general data memory, since they both have the same addressing capability. There are two data memory address points, RP0 (RP0H+RP0M+RP0L) and RP1 (RP1H+RP1M+RP1L), that can be operated by indirect addressing instructions, such as MOV ACC, @RP0 and MOV @RP1, @RP0, to move data between different data memory ranges and ACC. Instructions for moving data between ROM and RAM are also provided, such as MOV @RP0, @LUPC, so that users can move look-up table data in ROM to general RAM easily. The instruction MOV @RP0++, @LUPC++ is also available for automatically incrementing point counter by 1 once the instruction is completed. Please refer to instruction sets description for more details. The first 16 addresses (00H to 3FH) in the data memory are known as the page 0 working registers. Only working registers can directly operate with immediate data. A special register, WRPAGE, with ranges from 0H to 0DH, is used for selecting working register page. 2. Working Register Page (WRPAGE with SR=30H) WRPAGE, a 4-bit special register, that counts from 0 to 0DH, divides 896 nibbles RAM into 14 pages. Every page consists of 64 nibbles. The bit descriptions are as follow: 3 WRPAGE R/W 2 R/W 1 R/W 0 R/W
Bit 3~0: 0000~1011 Page 0 to Page 0DH Bit3~0: 0000~1111 is inhibited. All bits can be read/write. At initial reset, the WRPAGE is initiated to
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W53300/W53320
4 bits 00H 40H WRPAGE 0H WRPAGE 1H 64 nibbles 64 nibbles
896 address
. . . . . .
WRPAGE 7H
General RAM
200H WRPAGE 8H . .
WRPAGE 0CH 37FH WRPAGE 0DH 896 * 4 bits
LCD RAM
0000B..
Figure 2. Data Memory Mapping of W53320 3. RAM Point Register (RP0L, RP0M, RP0H, RP1L, RP1M, RP1L) There are two RAM points 0 and 1 that can be utilized for easily accessing data, either by direct or by indirect addressing. RAM Point 0 (RP0) is configured as 10-bit format (RP0.9~RP0.0) represented by 3 special registers, RP0L, RP0M and RP0H. RAM Point 1 (RP1) is configured as the same structure as RP0, thus are represented by RP1L, RP1M and RP1H. 11 RP0 X 10 X RP0H 11 RP1 X 10 X RP1H 9 8 7 9 8 7 6 5 4 3 2 1 0
RP0.9 RP0.8 RP0.7 RP0.6 RP0.5 RP0.4 RP0.3 RP0.2 RP0.1 RP0.0 RP0M 6 5 4 3 RP0L 2 1 0
RP1.9 RP1.8 RP1.7 RP1.6 RP1.5 RP1.4 RP1.3 RP1.2 RP1.1 RP1.0 RP1M RP1L
All bits of RPn are allowed for read/write operation. At initial reset, all RPn are cleared to 0000B.
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Publication Release Date: March 1999 Revision A2
W53300/W53320
Special Register and Special Register Pair (SR & SRP)
Some special registers are formatted as 4-bit in length, as shown in Table 2. Chip operating condition depends on the value of the special register. Commands such as MOV SR, #I, CLR SR and SET SR write the appropiate value to control chip operating state. Some special registers, such as HEF, IEF and HCF, can write 8-bit immediate data simultaneously by using commands associated with Special Register Pair (SRP) like MOV SRP, #I. All special register functions will be described in detail when the close relation function is introduced. SRP SR 00 01 02 03 04 05 06 07 08 09 0A 0B 06H 07H 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F SR Symbol --------TM0L(w) TM0H(w) TM1L(w) TM1H(w) TMC1L(r) TMC1H(r) --------EVFL(r,c) EVFH(r,c) Event Flag (set by chip hardware if interrupt is occurred) RD,RC,TM0,DIV TM1,SPEECH,MELODY,X RD,RC,TM0,DIV TM1,SPEECH,MELODY,X RD,RC,TM0,DIV TM1,SPEECH,MELODY,X RD,RC,TM0,DIV TM1,SPEECH,MELODY,X Function Bit 3 ~ 0 assignment
low nibble of Timer 0 high nibble of Timer 0 low nibble of Timer 1 high nibble of Timer 1 low nibble of Timer 1 high nibble of Timer 1
TM0.3~TM0.0 TM0.7~TM0.4 TM1.3~TM1.0 TM1.7~TM1.4 TM1.3~TM1.0 TM1.7~TM1.4
HEFL(r/w,s/c) Hold mode release Enable Flag HEFH(r/w,s/c) IEFL(r/w,s/c) IEFH(r/w,s/c) HCFL(r) HCFH(r) --------PEFL(r/w,s/c) PEFH(r/w,s/c) RP0L(r/w) RP0M(r/w) RP1L(r/w) RP1M(r/w) RP0H(r/w) RP1H(r/w) MLDL(w) MLDH(w) SPCL(w) SPCH(w) Interrup Enable Flag Hold mode release Condition Flag (set by H/W if hold mode is released)
Port Enable Flag for hold mode release or interrupt function RAM address Pointer 0 Low nibble RAM address Pointer 0 Middle nibble RAM address Pointer 1 Low nibble RAM address Pointer 1 Middle nibble RAM address Pointer 0 High nibble RAM address Pointer 1 High nibble MeLoDy score address Low nibble MeLoDy score address High nibble SPeeCh section address Low nibble SPeeCh section address High nibble
RC.3, RC.2, RC.1, RC.0 RD.3, RD.2, RD.1, RD.0 RP0.3~RP0.0 RP0.7~RP0.4 RP1.3~RP1.0 RP1.7~RP1.4 X,X, RP0.9,RP0.8 X,X, RP1.9,RP1.8 MLD.3~MLD.0 MLED1,MLED0, OSB,MLD.4 SPC.3~SPC.0 SPC.7~SPC.4
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W53300/W53320
20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B
CF(r,s/c) Carrier Flag ----FLAG0(r/w,s/c) melody/speech busy and play flag FLAG1(c) reset flag for Divider/WatchDog --------MR2(r/w,s/c) MR3(w) MR0(r/w,s/c) MR1(w) LCDM1(w) SCR(r/w,s/c) LUP0(r/w) LUP1(r/w) LUP2(r/w) LUP3(r/w) WRPAGE(r/w) LUC(r) PM0(r/w,s/c) ----PSR0(r,clr-all) PSR1(r,clr-all) PM1(r/w,s/c) PM2(r/w,s/c) PORTA(r/w) PORTB(r/w) PORTC(r) PORTD(r)
X,X,X,CF MLD_busy,SPC_busy,MLD_play,SPC_play X,DIVR,WDTR,X
special register for interrupt enable X,X,X,INTEN Mode register 3 for pump voltage and VLCDEXT,X,CUR1,CUR0 PWM current Mode Register 0 for timer Mode Register 1 for timer LCD Mode register 1 System Control Register Look UP table address pointer 1st nibble Look UP table address pointer 2nd nibble Look UP table address pointer 3th nibble Look UP table address pointer 4th nibble Working Register PAGE register LUPC nibble counter Port Mode Register 0 Port RC Status change Register Port RD Status change Register Port RA I/O Mode select Register Port RB I/O Mode select Register PORT data of RA PORT data of RB PORT data of RC PORT data of RD TM0EN,TM1EN,LCDEN,TONE WDTCK,TM0CK,TM1SR,TM1CK COM32B,BIAS7B,PUPV3B,INTSRB DIV5MB,FMRCB,FMEN,F32IN LUPC.3~LUPC.0 LUPC.7~LUPC.4 LUPC.11~LUPC.8 X,X,LUPC.13,LUPC.12 0000~1101H 0000~0100H RD_PH,RC_PH,RB_NM,RA_NM RC3EG~RC0EG RD3EG~RD0EG RA3IN~RA0IN RB3IN~RB0IN RA3~RA0 RB3~RB0 RC3~RC0 RD3~RD0 RE3~RE0
3C PORTE(w) PORT data of RE 3D~3F -----Note 1: "r, w, s, c " means "read, write, set, and clear" (respectively) Note 2: "clr-all " means all 4 bits will be cleared simultaneously. Note 3: X means don't care bit Table 2: Special Register address mapping
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Publication Release Date: March 1999 Revision A2
W53300/W53320
Accumulator (ACC)
The accumulator (ACC) is a 4-bit register used to hold results from the ALU, and to transfer data between the data memory, I/O ports, and special registers.
Arithmetic and Logic Unit (ALU)
ALU is a circuit which performs arithmetic and logic operations. It provides the following functions: * Logic operations: ANL, XRL, ORL * Branch decisions: JB0, JB1, JB2, JB3, JNZ, JZ, JC, JNC, DSKZ, DSKNZ, SKB0, SKB1, SKB2, SKB3, JNB0, JNB1, JNB2, JNB3, SKNB0, SKNB1, SKNB2, SKNB3 * Shift operations: SHRC, RRC, SHLC, RLC * Binary additions/subtractions: ADDC, ADD, ADDU, SUB, SUBB, DEC, INC After any of the above instructions is executed, the status of the carry flag (CF) will be affected. The CF will be stored into internal register, and read out by MOVA R, CF or MOV CF, R. Carry Flag Register (CF with SR=20H) The CF register stores only the CF signal state. Please refer to instruction sets for CF signal status. 3 CF X 2 X 1 X 0 CF
Clock Generator
W53300/W53320 provides two oscillation circuits: main-oscillator (FM) and sub-oscillator (FS). The SCR (System Control Register) is incorporated to specify clock operation condition. Either mainoscillator or sub-clock can be the system clock ( FOSC ) by setting F32IN option bit (bit 0 of SCR special register). The main-oscillator starts oscillation when FMEN (bit 1 of SCR) is set to 1. Mainoscillator can select crystal or RC oscillation through external connections by setting special register FMRCB bit (bit 2 of SCR). If a crystal oscillator is chosen, a crystal or a ceramic resonator must be connected between XIN and XOUT, and a capacitor must be connected if accurate frequency is required. The oscillator supports clock frequency from 400KHz to 4 MHz. A 455 KHz ceramic resonator should be selected if an IR carrier output from RE3/TONE is needed. On the other hand, if the RC oscillator is selected, a resistor must be connected between XIN and VDD. The sub-oscillator must be connected to a 32.768 KHz crystal between X32I and X32O. The connection is shown in Figure 3. One machine cycle consists of a four-state system clock sequence, and can run up to 1 S with a 4 MHz system clock.
VDD
RXIN XIN Crystal (400K to 4MHz ) or XOUT Crystal 32 KHz X32O X32I
Figure 3. Oscillator Configuration
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W53300/W53320
Dual-clock operation
This operation mode is dual-clock mode when FMEN bit is enabled. LCD operation clock source must be the sub-oscillator clock (32768 Hz) only. Sub-clock is used as system clock at initial reset, for example, power on or if reset pin is actived, since SCR special register is set to 0001B. However, if high frequency clock is required, that is, where main-clock should be selected as the system clock, a proper value should to be written to F32IN. The exchange of the main-clock and sub-clock operation is performed by resetting or setting F32IN. If F32IN is reset to 0, the clock source of the system clock generator is the main-oscillator clock; if the F32IN is set to 1, the clock source of the system clock generator is the sub-oscillator clock. The main-oscillator will stop oscillating when FMEN is reset to 0. Please attend to the setting or resetting of SCR register when: 1. XX10B XX01B: Disabling the main-oscillator (FM) should not be done at the same time as changing the system clock source (FOSC) from FM to FS. The FOSC should be changed from FM to FS before the main-oscillator (FM) is disabled. The correct seqence is: XX10BXX11BXX01B. XX01B XX10B: Enabling the main-oscillator (FM) should not be done at the same time as changing the system clock source (FOSC) from FS into FM. The main-oscillator (FM) should be enabled before a delay subroutine is called for stabilizing the main-oscillator; the FOSC can then be changed from FS into FM. The correct sequence is therefore XX01BXX11Bdelay subroutineXX10B. The suggested delay for FM is 3.5 mS for 455 KHz ceramic resonator and 0.8 mS for 4 MHz crystal.
2.
Remember that bits FMEN and F32IN of SCR register can not be reset (XX00B) at the same time, as this will cause a system shutdown. The organization of the dual-clock operation mode is shown below.
HOLD
SCR.0 (F32IN) XOUT XIN SCR.1 (FMEN)
Main Oscillator
enable
Fm (0) Fosc Fs(1)
System Clock Generator
T1 T2 T3 T4
type select SCR.2 (FMRCB)
(Fosc=Fs while initial reset)
LCD Frequency Selector
X32O X32I
FLCD
Sub-oscillator
Divider
SCR.3 (DIV5MS)
INT0 HCF.0
Figure 4. The Dual Clock Operation Mode Control Diagram
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Publication Release Date: March 1999 Revision A2
W53300/W53320
System Control Register (SCR with SR=2BH) SCR is a 4 bit register (SCR.3~SCR.0). The functions of the bits are shown below. 3 SCR 2 1 0 F32IN DIV5MB FMRCB FMEN
F32IN =0: FM is used as FOSC input =1: FS is used as FOSC input FMEN =0: FM oscillation is disabled =1: FM oscillation is enabled FMRCB =0: FM type is RC oscillation =1: FM type is XTAL oscillation DIV5MB =0 : Divider overflows periodically every 0.5 sec. =1: Divider overflows periodically every 0.125 sec. All bits can be read/write, set/clear by user. At initial reset, the SCR is initiated to 0001B.
Divider
There is one divider, a 14-bit/12bit binary up-counter designed to generate periodic interrupts. The divider is incremented by each clock (Fs). When an overflow occurrs, the divider event flag is set (EVF.0 = 1). The interrupt is executed if the divider interrupt enable flag is set (IEF.0 = 1), and the hold state is terminated when the hold release enable flag is set (HEF.0 = 1). There are two time periods (500mS & 125 mS) that can be selected by DIV5MB bit. DIV5MB is reset to 0 (default) for selecting 500 mS period time, and is set to 1 for 125 mS.
Watchdog Timer (WDT)
The watchdog timer (WDT) is incorporated to prevent the program from being affected by unexpected errors. The WDT function can be enabled by mask option, and the clock source can be chosen between Fosc/1024 and Fosc/16384 by WDTCK (bit 3 of MR1 special register). At initial reset, the WDTCK derives from FOSC/1024. WDT overflow occurrs when chip operation is out of control. In this case, the whole system will be reset. The content of the WDT can be cleared by the instruction CLR FLAG1, #0010B or CLR WDT. The input clock of the WDT can be switched to FOSC/16384 (or FOSC/1024) when WDTCK is written 1 (or 0). In normal operation, the application program must reset WDT (by CLR WDT) before it overflows. The WDT minimum overflow period is 500mS when the system clock (FOSC) is 32 KHz and WDT clock input is FOSC/1024. The organization of the watchdog timer is shown in Figure 5.
FLAG1 Register (FLAG1 with SR=23H) Divider and watchdog counter can be reset by CLR FLAG1, #I instruction. Instructions CLR DIV and CLR WDT can be used to clear DIVR bit and WDTR bit respectively. The bit descriptions are as follows.
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W53300/W53320
3 FLAG1 X
2 DIVR
1 WDTR
0 X
DIVR =0 no influence =1 Divider counter is clear WDTR=0 no influence =1 Watchdog timer is clear X means don't care value All bits can be cleared only. At initial reset, FLAG1 is set to 0000B.
Divider
Fs
Q1 Q2
...Q9
Q10 Q11 Q12 Q13 Q14
R R R R
HEF.0 Fs/16384 Fs/4096 (0) (1) SCR.3 (DIV5MB) S R Hold mode release (HCF.0) Q EVF.0 IEF.0 Divider interrupt (INT0)
Fosc
Q1
Q2
...Q9
Q10 Q11 Q12 Q13 Q14
R R R R
1. Reset 2. CLR EVF,#01H 3. CLR FLAG1,#0100B (CLR DIV)
Fosc/16384 (1) Fosc/1024 (0) MR1.3 (WDTCK) Enable /Disable Mask Option
WDT
Qw1 Qw2 Qw3 Qw4
R R R R
Overflow signal
System Reset
1. Reset 2. CLR FLAG1,#0010B (CLR WDT)
Figure 5. Organization of Divider and Watchdog Timer
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Timer/Counter
1. Timer 0 (TM0) Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be loaded into TM0 by executing the MOV TM0L(TM0H),R instruction. If the TM0 is down-counting, executing MOV TM0L(TM0H),R instruction will stop TM0, reset TM0EN option bit (bit 3 of MR0 special register) to 0, and load specified value to TM0. When TM0EN is set to 1, the event flag 1 (EVF.1) is reset and the TM0 starts to count. Timer 0 stops operating and generates an underflow (EVF.1 = 1) while it decreases to FFH. The interrupt is executed if the Timer 0 interrupt enable flag is set (IEF.1 = 1); the hold state is terminated if the hold release enable flag 1 is set (HEF.1 = 1). The Timer 0 clock input can select either FOSC/1024 or FOSC/4 by setting TM1CK (bit 2 of MR1 special register) to 1 or resetting TM1CK to 0. The organization of Timer 0 is shown in Figure 6. Example: If the Timer 0 clock input is FOSC/4 : Desired Time 0 interval = (preset value +1) x 4 x 1/FOSC If the Timer 0 clock input is FOSC/1024 : Desired Time 0 interval = (preset value +1) x 1024 x 1/FOSC Preset value: Decimal number of Timer 0 preset value
MR1.2 (TM0CK) Fosc/1024 Fosc/4 (1) (0)
1. Reset 2. CLR EVF,#02H 3. Reset TM0EN 4. MOV TM0L,R or MOV TM0H,R Disable (1) 8-Bit Binary Down Counter (Timer 0) Enable (0) MR0.3 (TM0EN) MOV TM0H,R MOV TM0L,R 1. Reset 2. CLR EVF,#02H 3.Set TM0EN 4 4 S R Q EVF.1
HEF.1 Hold mode release (HCF.1) IEF.1 Timer 0 interrupt (INT1)
Figure 6. Organization of Timer 0 2. Timer 1 (TM1) Timer 1 (TM1) is also a programmable 8-bit binary down counter, as shown in Figure 7. Timer 1 can be used as a counter to count external events or to output an arbitrary frequency to the RE3/TONE pin. The input clock source of Timer 1 can be internal or external, determined by TM1SR option bit (bit 1 of MR1 special register). The internal clock can be FOSC/64 or FOSC, selected by TM1CK option bit (bit 0 of MR1 special register). At initial reset, the Timer 1 clock input is FOSC. An external clock is attached via RC0 input pin. If an external clock is selected as the clock source of Timer 1, the content of Timer 1 is decreased by 1 at the falling edge of RC.0. Executing MOV TM1L, R or MOV TM1H,R
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W53300/W53320
instruction will load specified data to the auto-reload buffer and disable TM1 down-counting (i.e. TM1EN is reset to 0). If TM1EN is set to 1, the contents of the auto-reload buffer will be loaded into the TM1 down counter to start counting and reset the event flag 7 (EVF.7 = 0). When the timer decreases to FFH, it will generate an underflow (EVF.7 = 1) and will be auto-reloaded with the specified data, after which it will continue to count down. An interrupt is executed if the interrupt enable flag 7 is set to 1 (IEF.7 = 1), and the hold state is terminated if the hold mode release enable flag 7 is set to 1 (HEF.7 = 1). The specified frequency of Timer 1 can also be output to the RE3/TONE pin by TONE option bit (bit 0 of MR0). Example: If the Timer 1 clock input is FT : Desired Timer 1 interval = (preset value +1) / FT Desired frequency for RE3/TONE output pin = FT / (preset value + 1) / 2 (Hz) Preset value: Decimal number of Timer 1 preset value
MOV TM1H,R MOV TM1L,R
4
4 S Q EVF.7 1. Reset 2. INT7 accept 3. CLR EVF, #80H 4. Set TM1EN
MR0.2 (TM1EN) External clock via RC.0 Fosc/64 Fosc (1) (0) MR1.0 (TM1CK) (1) FT (0) MR1.1 (TM1SR) Enable (1)
Auto-reload buffer 8 bits 8-Bit Binary Down Counter (Timer 1)
R
Underflow signal
2
circuit
Reset
TONE (1) (0) PORTE.3 RE3/TONE output pin MR0.0 (TONE)
(0) Disable Reset Set TM1EN to 1
1. MOV TM1L, R or MOV TM1H, R 2. Reset TM1EN
Figure 7. Organization of Timer 1 For example, when FT equals 455kHz, depending on the preset value of TM1, the RE3/TONE pin will output a single tone signal in the tone frequency range from 889Hz to 227.5kHz. The relation between the tone frequency and the preset value of TM1 is shown in Table 3.
FT frequency TM1 Present value TONE output frequency
400KHz 04 40KHz
455KHz 05 37.9KHz
Table 3: TONE output
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Mode Register 0 (MR0 with SR=28H) Mode Register 0 is a 4-bit binary register (MR0.0 to MR0.3). The bit descriptions are as follows: 2 1 3 MR0 TM0EN TM1EN LCDEN 0 TONE
TONE = 0 RE3 as the data output of PORTE.3. = 1 RE3 will be as TONE signal output generated from Timer 1. LCDEN =0 LCD display OFF. =1 LCD display ON . TM1EN =0 Timer 1 counting is disabled. =1 Timer 1 counting is enabled. TM0EN=0 Timer 0 counting is disabled. =1 Timer 0 counting is enabled. User can read/write and set/clear all bits. At initial reset, MR0 is initiated to 0000B. Mode 1 Register (MR1 with SR=29H) Mode Register 1 is a 4-bit binary register (MR1.0 to MR1.3) . The bit descriptions are as follows: 2 0 1 3 MR1 WDTCK TM0CK TM1SR TM1CK TM1CK= 0 The internal Timer 1 clock rate is FOSC. = 1 The internal Timer 1 clock rate is FOSC/64. TM1SR=0 =1 Timer 1 with internal clock source (depended on TM1CK). Timer 1 with external clock source from RC0 pin.
TM0CK= 0 The internal Timer 0 clock rate is Fosc/4. = 1 The internal Timer 0 clock rate is FoSC/1024. WDTCK= 0 The watchdog timer clock rate is Fosc/1K. = 1 The watchdog timer clock rate is FoSC/16K. All bits can be written to by user. At initial reset, MR1 is set to 0000B.
Interrupts
W53300/W53320 provides five internal interrupt sources (Divider, TM0, SPEECH, MELODY and TM1) and two external interrupt sources (port RC and port RD). Vector addresses for each of the interrupts are located in the range of program memory (ROM) addresses from 004H to 020H. The flags IEF, PEF, and EVF are used to control the interrupts. When EVF is set to "1" by hardware and the corresponding bits of IEF and PEF are set by software, an interrupt is generated. When an interrupt occurs, all of the interrupts are inhibited until the EN INT or MOV IEF,#I instruction is invoked. The interrupts can also be disabled by executing the DIS INT instruction. When an interrupt is generated in hold mode, the hold mode will be released momentarily, and interrupt subroutine will be executed. After the RTN instruction is executed in an interrupt subroutine, the C will enter hold mode again. The control circuit diagram and operation flow chart are shown in Figure 8 and Figure 9 respectively.
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W53300/W53320
Mode Register 2 Register (MR2 with SR=26H) Mode Register 2 is a 1-bit only register . The INTEN bit of MR2 is used to disable/enable interrupt function. Instruction DIS EN can reset INTEN bit to logic 0, and EN INT sets INTEN bit to 1. 2 0 1 3 MR2 X INTEN X X INTEN = 0 Disable any interrupt process. = 1 Enable interrupt process where IEF.n is set by 1. X means don't care. User can use EN INT to set INTEN=1, and DIS INT to clear INTEN=0. At initial reset, MR2 is initialized to 0001B. Interrupt Enable Flag Register (IEF with SRP=07H) The interrupt enable flag (IEF) is an 8-bit binary register (IEF.0 to IEF.7), and comprises 2 registers IEFL (IEF.0~IEF.3) and IEFH (IEF.4~IEF.7) which are used for controlling the interrupt conditions. Instruction MOV IEF, #I deals with 8 bit immediate data, whereas MOV IEFH, #I and MOV IEFL, #I instructions deal with 4 bit immediate data. When one of the interrupts is accepted, the corresponding bit of the event flag will be reset by hardware, but the other bits are unaffected. In the interrupt subroutine, these interrupts will be disabled until the instruction MOV IEF, #I or EN INT is executed. Therefore, to enable these interrupts, the instructions MOV IEF, #I or EN INT must be executed again. These interrupts can be disabled by executing DIS INT instruction. The bit descriptions are as follows: 7 IEF TM1 6 5 X 4 3 RD 2 RC IEFL 1 TM0 0 DIV
Melody Speech
IEFH
IEF.0 = 1 Interrupt 0 is accepted by overflow from the Divider. IEF.1 = 1 Interrupt 1 is accepted by underflow from the Timer 0. IEF.2 = 1 Interrupt 2 is accepted by a signal change on port RC. IEF.3 = 1 Interrupt 3 is accepted by a signal change on port RD. IEF.4 Reserved IEF.5 = 1 Interrupt 5 is accepted when end of speech play with SPC_busy falling edge. IEF.6 = 1 Interrupt 6 is accepted when end of melody play with MLD_busy falling edge. IEF.7 = 1 Interrupt 7 is accepted by underflow from Timer 1. All bits can be read/write and set/clear by user.
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EN INT Divider overflow MOV IEF, #I S R Timer 0 underflow EVF.1 Q EVF.0
Initial Reset Enable
IEF.0
S R
Q
IEF.1 EVF.2 IEF.2 EVF.3 IEF.3 EVF.5 IEF.5 Interrupt Process Circuit Interrupt Vector Generator
004H 008H 00CH 010H 018H 01CH 020H
Port RC state change
S R
Q
Port RD state change
S R
Q
SPC_busy falling edge
S R
Q
MLD_busy falling edge
S R
Q
EVF.6 IEF.6 EVF.7 IEF.7 Initial Reset CLR EVF, #I instruction Disable
Timer 1 underflow
S R
Q
DIS INT instruction
Figure 8. Interrupt Event Control Diagram
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W53300/W53320
Figure 9. Hold Mode and Interrupt Operation Flow Chart
Hold Mode Operation
In hold mode, all operations of the C cease except for oscillator, timer, divider and LCD driver . The C enters hold mode once the HOLD instruction is executed. The hold mode can be released inone of seven ways, which are timer 0 underflow, timer 1 underflow, divider overflow, speech playing finished, melody playing finished, RC port pin state changed and RD port pin state changed. Before the device enters the hold mode, HEF, PEF, and IEF flags must be set to define the hold mode release conditions. For more details, refer to the instruction sets and Figure 9. Event Flag Register (EVFL, EVFH with SR=0AH & 0BH) EVFL (EVF.0 ~ EVF.3) and EVFH (EVF.4 ~ EVF.7) are 4 bit registers. It is set by hardware, and reset by instructions CLR EVFL,#I and MOV EVFH,#I or the occurrence of an interrupt. The bit descriptions are as follows:
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W53300/W53320
7 TM1
6
5 X
4
3 RD
2 RC EVFL
1 TM0
0 DIV
Melody Speech
EVFH EVF.0 = 1 Overflow from Divider. EVF.1 = 1 Underflow from Timer 0. EVF.2 = 1 State change on port RC. EVF.3 = 1 State change on port RD. EVF.4 Reserved.
EVF.5 = 1 End of speech play with SPC_busy flag falling edge. EVF.6 = 1 End of melody play with MLD_busy flag falling edge. EVF.7 = 1 Underflow from Timer 1 . All bits can be read and clear only by users. Hold Mode Release Enable Flag Register (HEF with SRP=06H) The hold mode release enable flag is a 8-bit register (HEF.0 to HEF.7), and comprises two registers HEFL (HEF.0 ~ HEF.3) and HEFH (HEF.4~ HEF.7). Register HEF is used to control the hold mode release conditions, through the use of instruction MOV HEF, #I with 8 bit immediate data, or MOV HEFH,#I and MOV HEFL,#I with 4 bit immediate data. The bit descriptions are as follows: 7 HEF TM1 6 5 X 4 3 RD 2 RC HEFL 1 TM0 0 DIV
Melody Speech
HEFH
HEF.0 = 1 Overflow from the Divider causes hold mode to be released. HEF.1 = 1 Underflow from Timer 0 causes hold mode to be released. HEF.2 = 1 State change on port RC causes hold mode to be released. HEF.3 =1 State change on port RD causes hold mode to be released HEF.5 = 1 End of speech play with SPC_busy flag falling edge causes hold mode to be released HEF.6 =1 End of melody play with MLD_busy flag falling edge causes hold mode to be released HEF.7 = 1 Underflow from Timer 1 causes hold mode to be released. All bits can be read/write and set/clear by users.
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W53300/W53320
Hold Mode Release Condition Flag Register (HCFL, HCFH with SR=10H & 11H ) HCF is a 8-bit register (HCF.0 to HCF.7), and consists of HCFL (HCF.0~HCF.3) and HCFH registers (HCF.4~HCF.7). The hold mode is released, and loaded by hardware. The content of HCF can be read by using the MOVA R, HCFL and MOVA R, HCFH instructions. When any of the HCF bits is "1," the hold mode will be released and the HOLD instruction will be invalid. HCF can be reset by instruction CLR EVFL/EVFH,#I (EVF.n = 0). When EVF.n or HEF.n is reset, the corresponding bits of HCF is reset simultneously by hardware. The bit descriptions are as follows: 7 HCF TM1 6 5 X 4 3 RD 2 RC HCFL 1 TM0 0 DIV
Melody Speech
HCFH
HCF.0 = 1 Hold mode was released by overflow from the Divider. HCF.1 = 1 Hold mode was released by underflow from the Timer 0. HCF.2 = 1 Hold mode was released by a state change on port RC. HCF.3 = 1 Hold mode was released by a state change on port RD. HCF.4 reserved HCF.5 = 1 Hold mode was released when end of speech play with SPC_busy falling edge HCF.6 = 1 Hold mode was released when end of melody play with MLD_busy falling edge HCF.7 = 1 Hold mode was released by underflow from the Timer 1 All bits are read only by users, and set/clear by chip hardware.
Input/Output Ports RA, RB
Port RA consists of 4 pins RA0 to RA3, and port RB also consists of 4 pins RB0 to RB3. At initial reset, RA and RB input/output ports are both in input mode. When RA and RB are used as output ports, CMOS or NMOS open drain output type can be selected by the PM0 special register. Each pin of port RA or RB can be specified as input or output mode independently by PM1 and PM2 special registers. The MOVA R, PORTA and MOVA R, RORTB instructions operate the input functions, as MOV PORTA, R and MOV PORTB, R operate the output functions. For more details, refer to the instruction table and Figure 10. Port Mode 0 Register (PM0 with SR=32H) PM0 is a 4-bit register (PM0.0 to PM0.3). It can be used to determine the structure of the input/output ports; it is controlled by the MOV PM0, #I instruction. The bit descriptions are as follows: 3 PM0 2 1 0
RD_PH RC_PH RB_NM RA_NM
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RA_NM = 0 RA port is CMOS output type. = 1 RA port is NMOS open drain output type. RB_NM = 0 RB port is CMOS output type. = 1 RB port is NMOS open drain output type. RC_PH = 0 RC port pull-high resistor is disabled. = 1 RC port pull-high resistor is enabled. RD_PH = 0 RD port pull-high resistor is disabled. = 1 RD port pull-high resistor is enabled. All bits can be read/write and set/clear by user. At initial reset, PM1 is initialized to 0000B , where port RA and RB are of type CMOS input mode; port RC and RD are disabled pull-high resistors. Port Mode Register 1 and 2 (PM1, PM2 with SR=36H, 37H) PM1 (PM1.0 ~ PM1.3) and PM2 (PM2.0~PM2.3) are 4-bit registers. PM1 is used to control the input/output mode of port RA, using the instruction MOV PM1, #I. PM2 is used to control the RB input/output mode of port RB, using the instruction MOV PM2, #I. The bit descriptions are as follows: 3 2 1 0 PM1 RA0IN = 0 =1 RA1IN = 0 =1 RA2IN = 0 =1 RA3IN = 0 =1 RA3IN RA2IN RA1IN RA0IN
RB0 works as output pin; RB.0 works as input pin RB1 works as output pin; RB.1 works as input pin RB2 works as output pin; RB.2 works as input pin RB3 works as output pin; RB.3 works as input pin 3 2 PM2 RB3IN RB2IN
1 RB1IN
0 RB0IN
RB0IN = 0 RB0 works as output pin; = 1 RB.0 works as input pin RB1IN = 0 RB1 works as output pin; = 1 RB.1 works as input pin RB2IN = 0 RB2 works as output pin; =1 RB.2 works as input pin RB3IN = 0 RB3 works as output pin; = 1 RB.3 works as input pin All bits can be read/write and set/clear by users. At initial reset, port RA, RB is in input mode (PM1 = PM2 = 1111B).
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W53300/W53320
Port A Register (PORTA with SR=38H) PORTA register stores the current port RA pin state, and can be operated by MOV PORTA, R and MOV R, PORTA instructions. When port A is in input mode, it is read only. Otherwise a write operation is performed during RA ouput mode. 3 PORTA PA3 2 PA2 1 PA1 0 PA0
Port B Register (PORTB with SR=39H) PORTB register stores the current port RB pin state, and can be operated by MOV PORTB, R and MOV R, PORTB instructions. When port B is in input mode, it is read only. Otherwise a write operation is performed during RB ouput mode. 3 PORTB PB3 2 PB2 1 PB1 0 PB0
Input/Output Pin of the RA & RB
RA_NM (PM0.0) RB_NM (PM0.1)
&
Output Buffer DATA BUS
Enable
I/O PIN RAn & RBn
RAnIN RBnIN (PM1.n) & (PM2.n)
MOV PORTA, R (MOV PORTB, R) instruction
Enable
MOVA R, PORTA (MOVA R, RORTB) instruction
Figure 10. Architecture of RA ( RB) Input/Output Pins
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W53300/W53320
Input Ports RC, RD
Port RC consists of 4 pins RC0 to RC3, just as port RD consists of 4 pins RD0 to RD3. Each pin of port RC and port RD can be connected to a pull-up resistor, which is controlled by the port mode 0 register (PM0). When the bits of PEF, HEF, and IEF corresponding to the RC (RD) port are set, a state change at the specified pins of port RC (RD) will execute the hold mode release or interrupt subroutine. PSR0 and PSR1 record the signal changing status of the port RC and RD. PSR0 can be read and cleared by the MOVA R, PSR0 and CLR PSR0 instructions. PSR1 can be read and cleared by the MOVA R, PSR1 and CLR PSR1 instructions. Refer to Figure 11 and the instruction sets for more details. Port Enable Flag for hold mode (PEFL, PEFH with SR=14H, 15H) PEFL (PEFL.3~PEFL.0) and PEFH (PEFH.3~PEFH.0) are 4 bit registers. PEFL controls port RC status, and PEFH is responsed for port RD status. Before port RC or RD is used to release the hold mode or to perform an interrupt function, the content of the PEFL/PEFH must be set first. If PEFL/PEFH is written to "1", the function will be enabled. Instructions MOV PEFH,#I and MOV PEFH,#I can be used with 4 bit immediate data. The bit descriptions are as follows: 3 2 1 0
PEFL PEFL.3 PEFL.2 PEFL.1 PEFL.0 PEFL.0 =1 : State change on pin RC0 to release hold mode or perform interrupt PEFL.1 =1 : State change on pin RC1 to release hold mode or perform interrupt PEFL.2 =1 : State change on pin RC2 to release hold mode or perform interrupt PEFL.3 =1 : State change on pin RC3 to release hold mode or perform interrupt 3 2 1 0
PEFH PEFH.3 PEFH.2 PEFH.1 PEFH.0 PEFH.0 =1 : State change on pin RD0 to release hold mode or perform interrupt PEFH.1 =1 : State change on pin RD1 to release hold mode or perform interrupt PEFH.2 =1 : State change on pin RD2 to release hold mode or perform interrupt PEFH.3 =1 : State change on pin RD3 to release hold mode or perform interrupt All bits can be read/write and set/clear by users. Port Status Register 0 and 1 (PSR0, PSR1 with 34H, 35H) PSR 0 (PSR0.0 to PSR0.3) and PSR1 (PSR1.0 to PSR1.3) are 4-bit registers. They are set to "1" if PEF.n is enabled and RCn (RDn) input state is changed. Then hold mode or interupt will occur. Refer to Figure 10. PSR0 can be read or cleared by instructions MOVA R, PSR0, and CLR PSR0. PSR1 can be read or cleared by instructions MOVA R, PSR1, and CLR PSR1. The bit descriptions are as follows:
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W53300/W53320
3
2
1
0
PSR0 RC3EG RC2EG RC1EG RC0EG
Bit 0 = 1 : =0: Bit 1 = 1 : =0: Bit 2 = 1 : =0: Bit 3 = 1 : =0: RC0 input signal state is changed RC0 input signal state isn't changed RC1 input signal state is changed RC1 input signal state isn't changed RC2 input signal state is changed RC2 input signal state isn't changed RC3 input signal state is changed RC3 input signal state isn't changed
All bits are read only, and are cleared simultaneously. At initial reset , PSR1 is set to 0000B.
3 2 1 0
PSR1 RD3EG RD2EG RD1EG RD0EG
Bit 0 = 1 : RD0 input signal state is changed = 0 : RD0 input signal state isn't changed Bit 1 = 1 : RD1 input signal state is changed = 0 : RD1 input signal state isn't changed Bit 2 = 1 : RD2 input signal state is changed = 0 : RD2 input signal state isn't changed Bit 3 = 1 : RD3 input signal state is changed = 0 : RD3 input signal state isn't changed All bits are read only, and are cleared simultaneously. At initial reset , PSR1 is set to 0000B. Port C Register (PORTC with SR=3AH) This register stores the port RC current input state, which is specified by MOV R, PORTC instruction. 2 0 1 3 PORTC PC3 PC2 PC1 PC0
Port D Register (PORTD with SR=3BH) This register stores the port RD current input state, which is specified by MOV R, PORTD instruction. 2 0 1 3 PORTD PD3 PD2 PD1 PD0
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Output Port RE
When instruction MOV PORTE, R is executed, the data in the RAM will be output to port RE. The RE3 pin can be used to output TONE from Timer 1 if TONE option bit is set to 1. Port E Register (PORTE with SR=3CH) This register stores the current Port RE output state, which is specified by the MOV PORTE, R instruction. 3 PORTE PE3 2 PE2 1 PE1 0 PE0
DATA BUS PM0.2 (PM0.3) RC.0 (RD.0) Signal change detector PEF.0 (PEF.4) (PSR1.0) PSR0.0 Q ck R
D
PM0.2 (PM0.3) RC.1 (RD.1) Signal change detector
PEF.1 (PEF.5)
D Q ck R
(PSR1.1) PSR0.1
(EVF.3) EVF.2 D ck R Q
HEF.2
(HEF.3)
HCF.2 (HCF.3)
IEF.2 (IEF.3)
PM0.2 (PM0.3) RC.2 (RD.2) Signal change detector
PEF.2 (PEF.6)
D Q ck R
(PSR1.2) PSR0.2
INT 2 (INT3) CLR EVFL, #0100B (CLR EVFL, #1000B)
Reset
PM0.2 (PM0.3) PEF.3 (PEF.7) Signal change detector (PSR1.3) PSR0.3 Q ck R
D
RC.3 (RD.3)
Reset MOV PEF, #I CLR PSR0 (CLR PSR1)
Figure 11. Architecture of Input Ports RC (RD)
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W53300/W53320
Reset Function
W53300/W53320 is reset either by a power-on reset or RES active low pulse. Table 4 shows the initial reset state of internal special register and Input/Output. Program Counter (PC) Input/output ports RA, RB Output port RE RA & RB ports output type RC & RD ports pull-high resistors System Clock Input Timer 0 input clock Timer 1 input clock Input clock of the watchdog timer LCD display LCD Bias LCD Duty LCD Internal Pump Circuit LCD Pump Voltage SCR register MR2 register (INTEN flag) MR3 register PM1,PM2 register Others Registers Table 4: Default value at initial reset 0000B Input mode 0000B CMOS type Disable Fs (32768HZ) FOSC/4 FOSC FOSC/1024 OFF 1/7 bias 32 duty Enable Triple pump 0001B 0001B 0000B 1111B 0000B
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PART B: SPEECH and MELODY FUNCTION
Both speech and melody use the same clock source from ROSC pin. When speech or melody is playing, the ROSC clock is enabled, otherwise it is disabled for power saving. Speech synthesizer, just like melody sound tone, can be output to PWM1 and PWM2, thus directly driving the speaker. MR3 register assigns 2 bits (CUR1~CUR0) to control PWM current option. Speech coding can select whether two LED output pins (LED1 and LED2) will be active. LED1 can also be activated by melody depending on its output volume. However, speech and melody can not play at the same time. Therefore, users should require W53300/W53320 to play either speech sound or melody sound.
Mode Register 3 ( MR3 with SR=27H )
The MR3 register is used to enable internal LCD voltage pump circuit and PWM current output option. While VLCDEXT is disabled, PMPV3B bit option has meaning. On clearing VLCDEXT bit, the built-in LCD voltage pump circuit generates VDD2 and VDD3 from VDD. However, if VLCDEXT is set, an external power source needs to be added to VDD3 pin to generate common and segment output voltage. 3 MR3 VLCDEXT . CUR1~0: select PWM output driving current type 00: 5mA driving capability 01: 10mA driving capability 10: 15mA driving capability 11: 20mA driving capability VLCDEXT = 0 VDD3 is output pin, enabling internal LCD voltage pump circuit = 1 VDD3 is input pin, connecting external power source to VDD3 for com/segoutput MR3 register is write only. At initial reset, MR3 bit is set to 0000B.
FLAG0 Register (FLAG0 with SR=22H)
2 X
1 CUR1
0 CUR0
FLAG0 is a 4-bit register used to control the speech and melody synthesizers. FLAG0.1~0 can be read or written to, set or cleared by user, but FLAG0.3 ~ FLAG0.2 are set and cleared by chip hardware. At initial reset, FLAG0 is initialized to 0000B. Bits are defined as follows.
3 2 1 0
FLAG0
MLD_busy SPC_busy MLD_play SPC_play
SPC_paly =0 : Speech play is disabled. =1 : Speech play is enabled while SPC_play high keeps 8 Tcyc minimum. MLD_paly =0 : Melody play is disabled. =1 : Melody play is enabled while MLD_play high keeps 30ms minimum. SPC_busy =0 : Speech play is finished. =1 : Speech play is processing. MLD_busy =0 : Melody play is finished. =1 : melody play is processing.
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W53300/W53320
SPEECH Function
Speech synthesizer is built-in 384 K bits dedicated speech ROM, which can be separated by Winbond ADPCM Power Speech Coding System to a maximum of 256 sections with different voices. In order to play speech voice, the playing section number needs to be written to SPCH and SPCL, and SPC_play option bit (bit 0 of FLAG0 special register) set to 1. Then SPC_busy bit (bit 2 of FLAG0) will be changed from low to high, and remains high till speech play comes to an end. If interrupt flag (IEF.5) or hold mode flag (HEF.5, HCF.5) is set, interrupt or hold mode release will be processed when SPC_busy falling edge occurs. The circuit structure is shown in Figure 12. SPC_play bit can be set to "1" again, after finishing transfer of section number via parallel to serial interface during previous SPC_play edge. There is minimum 8-instruction delay between two continuous SPC_play rising. Two LED outputs with 3Hz frequency can be used to drive external LED during speech playing. The SPCH and SPCL will be latched during SPC_play risng edge. The speech synthesizer is disabled when MLD_busy bit (bit 3 of FLAG0) is 1, and so is the melody synthesizer when SPC_busy bit is 1. The SPC_play is set to 1 to activate the speech synthesizer. The speech synthesizer receives the rising edge of SPC_play, then plays the voice section pointed by SPC.7~SPC.0 and sets SPC_busy to logic 1. The SPC_busy is cleared by hardware if the speech synthesizer finishes its tasks or executes an END section. The END section number can be defined by speech programmer at any section.
Parallel to serial Interface Section Num. 8
CLK
TG1 TG2 TG3
VDD D CK R Q
HEF.5 Hold mode release (HCF.5) IEF.5 EVF.5 Speech interrupt (INT5)
W 528X
SPC Register
4 4 SPC_play (FLAG0.0 bit) rising edge
min 8 Tcyc
1. Reset 2. CLR EVFH,#0010B 3.MOV FLAG0,#0001B
MOV SPCH, RL
MOV SPCL, RL
Figure 12. Speech Circuit Diagram
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Publication Release Date: March 1999 Revision A2
W53300/W53320
Speech Section Register (SPCL, SPCH with SR=1EH & 1FH) The SPCH and SPCL registers named as SPC.7 ~SPC.0 define the speech section that the speech synthesizer is to play. SPCH (SPC.7 ~ SPC.4) represents the high nibble as SPCL (SPC.3 ~ SPC.0) represents the low nibble. When actived, the speech synthesizer plays the voice section pointed by SPC.7~SPC.0 with maximum 256 sections (00h to FFh). 7 SPC SPC.7 6 SPC.6 5 4 3 2 1 0 SPC.0
SPC.5 SPC.4 SPC.3
SPC.2 SPC.1 SPCL
SPCH
Melody Function
Dual tone melody is dedicated ROM with built-in tremolo function , 3 percussions, 6 beats, 41 pitches from G3# to C7, 16 kinds of tempo and 1K notes (22 bits per note), which can be separated to a maximum of 32 different scores. The dual tone melody is played using the same methodology as speech, but including END command. The melody scores can be written to MLDH and MLDL registers. Then MLD_play is enabled high to play melody, and the MLD_busy bit will be changed from low to high and remains high till melody play is ended. If interrupt flag (IEF.6) or hold mode flag (HEF.6, HCF.6) is set, interrupt or hold mode release will be processed when MLD_busy falling edge occurs. The MLDH and MLDL will be latched during MLD_play rising edge. Users can select melody play mode using the OSB bit (bit 1 of MLDH). In one-shot trigger mode (OSB=0), the melody synthesizer receives a rising edge of MLD_play, then plays the score pointed by MLD4~MLD.0, and sets the MLD_busy to logic 1. When the melody synthesizer finishes its tasks or receives a rising edge of MLD_play with score number with END command, the melody synthesizer enters the standby mode and MLD_busy is pulled to logic 0. In level-trig mode (OSB=1), the melody synthesizer plays the pointed score when MLD_busy is set to 1. The MLD pointed score is repeatedly played and the MLD_busy is pulled high until the MLD_play is cleared by user. Bits MLED1 and MLED0 of the MLDH register can be used to control the LED1 pin output timing while melody is playing, where LED1 output is a volume control by melody tone.
enable LED
(MLED1,MLED0) 2 5
Score Address
VDD D CK R Q
HEF.6 EVF.6 IEF.6
Hold mode release (HCF.6) Speech interrupt (INT6)
1
MLD_play (FLAG0.1 bit)
OSB
MLD Register
4 4
Melody
1. Reset 2. CLR EVFH,#0100B 3.MOV FLAG0,#0010B
MLD_play
MOV MLDH, #I
MOV MLDL,#I
Tmld :min 30ms
Figure 13. Melody Circuit Diagram
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W53300/W53320
Melody Scores Register (MLDL, MLDH with SR=1CH, 1DH) MLD register is made up of two 4-bit registers, MLDH and MLDL. MLDH represents the high nibble (MLED1, MLED0 , OSB, MLD.4), while MLDL represents the low nibble (MLD.3 ~ MLD.0). Bit MLD.4 to bit MLD.0 together form a 5-bit pointer of scores. MLED1 and MLED0 is used to control LED1 pin active type during melody playing. When actived, the melody synthesizer plays the score section pointed by the MLD.4 ~ MLD.0 . 31 scores, from score 01H to score 1FH, can be pointed by the MLD register. When the melody synthesizer is on one-shot trigger mode and MLD.4 ~ MLD.0 is set to 00H, a melody-play command becomes a melody-stop command. 7 MLD MLED1 6 MLED0 5 4 3 2 1 0 MLD.0
OSB MLD.4 MLD.3
MLD.2 MLD.1 MLDL
MLDH
MLD.4 ~ MLD.0 are the melody score number with maximum 31 scores. OSB=0 : Melody play mode by one shot trigger =1 : Melody play mode by level trigger MLED1~0: Select LED1 output pin active type while melody is playing. 00: LED1 is disabled while melody is playing 01: LED1 will be active when melody volume is higher than low level 10: LED1 will be active when melody volume is higher than middle level 11: LED1 will be active when melody volume is higher than high level
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Publication Release Date: March 1999 Revision A2
W53300/W53320
PART III: LCD FUNCTION
W53300/W53320 can directly drive an LCD panel with 16/32 common output pins and 48 segment output pins for a total of 32 x 48 dots. The updating rate per frame is 64 Hz. Two registers, LCDM1 and MR3.3 (refer to page MR3 description) can be used to select different LCD operating types, such as duty cycle, bias ratio, maximum pump voltage, internal shunt resistor, and enable LCD pump voltage circuit, by using instructions MOV LCDM1, #I, MOV LCDM1, RL (where RL is the low 9 bit of RAM address ) and MOV LCDM1, ACC. For power saving, one can use LCDON and LCDOFF instructions, to turn the LCD display on and off. This is done by controlling the LCDEN bit (bit 1 of MR0 register). The LCD display can be turned on even in HOLD mode. At initial reset, LCDM1 register is initiated to 0000B. This sets the LCD operating condition to 1/16 or 1/32 duty, 1/5 or 1/7 bias, triple pump voltage with internal shunt resistor, and lights up all the LCD segments. Upon the end of the initial reset state, the LCD display is turned off automatically. The circuit architecture is shown in Figure 14. Different application conditions are shown in Figures 15 to 19.
Fs Data Bus
MOV R, #I Instruction
Clock Generator
LCDM1 Register
DH1 DH2 VDD2 VDD3
LCD PUMP Voltage
PMPV3B (LCDM1.1) VLCDEXT (MR3.3) COM32B (LCDM1.3)
LCD Data RAM (32 x 48 bits)
BIAS7B(LCDM1.2) INTSRB (LCDM1.0)
LCDEN(MR0.1)
FLCD LCD Shunt Resistor Commom Driver Segment Driver
V2 to V6
COM0 to 31
SEG0 to 47
Figure 14. LCD Driver Circuit Diagram
LCD Pattern RAM (LCDR000H~LCDR17FH)
Corresponding to 48 LCD drive output pins, there are 384 LCD data RAM (LCDR). The address of LCD data RAM, which can be addressed by LCDR000 to LCDR17F, is mapping to address from 200H to 37FH of general purpose RAM. In fact, LCD data RAM are also general purpose RAM, and all instructions that are applied to RAM 00H~1FFH are also applied to LCDR. Therefore, the unused portions of LCD RAM can be used as general purpose data RAM. Instructions such as MOV LCDR,#I, MOV WR, LCDR, MOV LCDR,WR and MOV LCDR, ACC are provided to control the LCD data RAM, as the assembler will interpret LCDR as RAM by automatically adding 1FFH. Writing 1 to bit value of LCD data RAM will turn the LCD dot on; nevertheless 0 turns off the LCD dot. The contents of the LCD data RAM are sent out to the SEG0~SEG47 pins by a direct memory access. The relation between the LCD data RAM and segment/common pins is shown in Table 5.
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W53300/W53320
LCD DATA RAM LCDR000 ( RAM200 ) LCDR001 ( RAM201 ) LCDR002 ( RAM202 ) LCDR003 ( RAM203 ) LCDR004 ( RAM204 ) LCDR005 ( RAM205 ) LCDR006 ( RAM206 ) LCDR007 ( RAM207 ) LCDR008 ( RAM208 ) LCDR009 ( RAM209 ) LCDR00A ( RAM20A ) LCDR00B ( RAM20B ) LCDR00C ( RAM20C ) LCDR00D ( RAM20D ) LCDR00E ( RAM20E ) LCDR00F ( RAM20F ) : : LCDR378 ( RAM378 ) LCDR379 ( RAM379 ) LCDR37A ( RAM37A ) LCDR37B ( RAM37B ) LCDR37C ( RAM37C ) LCDR37D ( RAM37D ) LCDR37E ( RAM37E ) LCDR37F ( RAM37F )
OUTPUT PIN
BIT3 COM3 COM7 COM11 COM15
BIT 2 COM2 COM6 COM10 COM14 COM18 COM22 COM26 COM30 COM2 COM6 COM10 COM14 COM18 COM22 COM26 COM30 : : COM2 COM6 COM10 COM14 COM18 COM22 COM26 COM30
BIT 1 COM1 COM5 COM9 COM13 COM17 COM21 COM25 COM29 COM1 COM5 COM9 COM13 COM17 COM21 COM25 COM29 : : COM1 COM5 COM9 COM13 COM17 COM21 COM25 COM29
BIT 0 COM0 COM4 COM8 COM12 COM16 COM20 COM24 COM28 COM0 COM4 COM8 COM12 COM16 COM20 COM24 COM28 : : COM0 COM4 COM8 COM12 COM16 COM20 COM24 COM28
SEG0
COM19 COM23 COM27 COM31 COM3 COM7 COM11 COM15
SEG1
COM19 COM23 COM27 COM31
: :
: : COM3 COM7 COM11 COM15
SEG47
COM19 COM23 COM27 COM31
Table5. LCD RAM mapping to segment and common output pins
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Publication Release Date: March 1999 Revision A2
W53300/W53320
LCD Mode Register 1 (LCDM1 with SR=2AH)
LCDM1 is a 4-bit register (LCDM1.0 ~ LCDM1.3) for selecting LCD duty cycle, bias ratio, pump voltage and internal shunt resistor, by using the instructions MOV LCDM1, #I, MOV LCDM1, RL" (where RL is the low 9 bit of RAM address ) and MOV LCDM1, ACC. Bit 3 of LCDM1, COM32B defines the duty cycle. Bit 2, known as BIAS7B, controls bias ratio to match the characteristics of the LCD panel. Bit 1, PMPV3B, is used to choose the maximum output voltage (either a doubler or a tripler) of COM/SEG, when the build-in LCD voltage pump circuit is enabled. The voltage tripler should be enabled for 3V operating voltage, and the voltage doubler for 4.5V operating voltage. Bit 0, defined as INTSRB, is used to select the internal shunt reistor for V2~V6 output power. Diagrams below show the application circuits; output waveforms of the five LCD driving modes are shown in Figures 14 to 25. 3 2 1 0 LCDM1 COM32B BIAS7B INTSRB = 0 =1 PMPV3B = 0 =1 BIAS7B = 0 =1 COM32B =0 =1 PMPV3B INTSRB
Internal shunt resistor is available between V2~V6 External shunt resistor is needed between V2 ~V6. Triple pump voltage available (recommended when VDD=3v) Double pump voltage available (recommended when VDD=4.5v) 1/7 bias available (recommended for 32 common) 1/5 bias available (recommended for 16 common) 1/32 duty, COM0~COM31 output available 1/16 duty, COM0~ COM15 output available
All bits are write only. At initial state, LCDM1 is cleared to 0000B.
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W53300/W53320
External VLCD (4)
(VLCD<3*VDD) V6 C4 R V5 C5 R VDD V4 C6 C7 R'
(2)
VDD3 C2 VDD2 C3 C H I P + C1 DH2
VDD = 3V
DH1
V3 R V2 C8
(3)
R
(1)
VSS
(1) R=10k~20komh if INTSRB bit =1 (2) R'=R for 1/5 bias R'=3*R for 1/7 bias (3) C4~C8 option (4) C1~C2 can be skipped if external VLCD exists.
Figure 15. Triple pump voltage
External VLCD (4)
(VLCD<2*VDD) V6 C4 R V5 C5 R VDD V4 C6 C7 R' (2) V3 R V2 C8
(3)
VDD3 C2 VDD2
C H I P
+ C1
VDD = 4.5V
DH1 DH2
R (1) VSS
(1) R=10k~20komh if INTSRB bit =1 (2) R'=R for 1/5 bias R'=3*R for 1/7 bias (3) C4~C8 option (4) C1~C2 can be skipped if external VLCD exists.
Figure 16. Double pump voltage
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Publication Release Date: March 1999 Revision A2
W53300/W53320
LCD Example and Waveform:
On the basis of the Figure 17 pattern assignment, the common, segment output waveform can be obtained as shown in Figure 18 for 1/7 bias, and in Figure 19 for 1/5 bias.
C0 C1 C2
a b c
C14 C15 16 com
d (C30) (C31) S0 S1 S10 is dot on e
32 com
S47
S48
Note:
is dot off and
Figure 17. Common/Segment driving pattern
- 40 -
W53300/W53320
V5
.......
COM0
V2
V6 V5 V4 V3 V2 VSS V6 V5 V4 V3 V2 VSS V6 V5 V4 V3 V2 VSS
.......
V5
.......
COM1
V2
.......
V5
.......
COM31
V2
.......
V4
SEG0 (All dot OFF)
V3
....... .......
V6 V5 V4 V3 V2 VSS V6 V5 V4 V3 V2 VSS VSS V6 V5 V4 V3 V2 VSS
.......
V6
SEG1 (All dot ON)
VSS
.......
V6
SEG10 (dot a,c,e ON)
V3 VSS
....... .......
negative frame
V4
postive frame frame rate =64 Hz
V6 V5 V4
C31-S10 (dot e ON)
V2 -V2 .......
.......
V3 V2 VSS -V2 -V3 -V4 -V5 -V6
Figure 18. 1/7 bias, 1/32 duty driving waveform
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Publication Release Date: March 1999 Revision A2
W53300/W53320
COM0
V2
V5
.......
.......
V5
V6 V5 V4 V3 V2 VSS V6 V5 V4 V3 V2 VSS V6 V5 V4 V3 V2 VSS
COM1
V2
.......
.......
V5
COM15
V2
.......
.......
negative frame frame rate =64 Hz V4
positive frame frame rate =64 Hz
SEG0 (All dot OFF)
V3
...... .
....... .......
V6 V5 V4 V3 V2 VSS V6 V5 V4 V3 V2 VSS
V6
SEG1 (All dot ON)
VSS
.......
V6
SEG10 (dot a,c,e ON)
V3 VSS V6
.......
V4
.......
V6 V5 V4 V3 V2 VSS V6 V5 V4 V3 V2 VSS -V2 -V3 -V4 -V5 -V6
C0-S10 (dot a ON)
.......
V2
VLCD
.......
-V6
-V2
-VLCD
Figure 19. 1/5 bias, 1/16 duty driving waveform
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W53300/W53320
TYPICAL APPLICATION CIRCUIT
- 43 -
Publication Release Date: March 1999 Revision A2
W53300/W53320
INSTRUCTION SET SUMMARY
Symbol Description
WR SR SRP ACC acc.n R R.n RL RL.n P @P @P.n LUPC @LUPC I or i: L CF PC == !=
Working RAM Special register Special register pair Accumulator Accumulator bit n Data Memory address from RAM000~RAM3FF Bit n of data memory from RAM000~RAM3FF Data Memory address from RAM000~RAM1FF Bit n of data memory from RAM000~RAM1FF RAM pointer rp0/rp1 Memory (RAM) addressed by pointer rp0/rp1 Memory (RAM) bit n addressed by pointer rp0/rp1 ROM pointer, for use with look-up-table Memory (ROM) addressed by pointer lupc Constant parameter Branch or jump address Carry Flag Program Counter Equal Not equal AND OR Exclusive OR Transfer direction, result
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W53300/W53320
Mnemonic
Des/Src operand R, ACC @P, ACC WR, #I @P, #I ACC, #I
Affected flag CF
function description ACC R + ACC. ACC @P + ACC. ACC WR + I. ACC @P + I. ACC ACC + I.
ADD
ADDC
R, ACC @P, ACC WR, #I @P, #I ACC, #I
CF
ACC R + ACC + CF. ACC @P + ACC + CF. ACC WR + I + CF. ACC @P + I + CF. ACC ACC + I + CF.
ADDU
R, ACC @P, ACC WR, #I @P, #I ACC, #I
--
ACC R + ACC. ACC @P + ACC. ACC WR + I. ACC @P + I. ACC ACC + I.
ADDUR
R, ACC @P, ACC WR, #I @P, #I
--
ACC, R R + ACC. ACC, @P @P + ACC. ACC, WR WR + I. ACC, @P @P + I.
ADDR
R, ACC @P, ACC WR, #I @P, #I
CF
ACC, R R + ACC. ACC, @P @P + ACC. ACC, WR WR + I. ACC, @P @P + I.
ADDCR
R, ACC @P, ACC WR, #I @P, #I
CF
ACC, R R + ACC + CF. ACC, @P @P + ACC + CF. ACC, WR WR + I + CF. ACC, @P @P + I + CF.
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Publication Release Date: March 1999 Revision A2
W53300/W53320
SUB
R, ACC @P, ACC WR, #I @P, #I ACC, #I
CF
ACC R - ACC. ACC @P - ACC. ACC WR - I. ACC @P - I. ACC ACC - I.
SUBB
R, ACC @P, ACC WR, #I @P, #I ACC, #I
CF
ACC R - ACC - CF. ACC @P - ACC - CF. ACC WR - I - CF. ACC @P - I - CF. ACC ACC - I - CF.
SUBR
R, ACC @P, ACC WR, #I @P, #I
CF
ACC, R R - ACC. ACC, @P @P - ACC. ACC, WR WR - I. ACC, @P @P - I.
SUBBR
R, ACC @P, ACC WR, #I @P, #I
CF
ACC, R R - ACC - CF. ACC, @P @P - ACC - CF. ACC, WR WR - I - CF. ACC, @P @P - I - CF.
ANL
R, ACC @P, ACC WR, #I @P, #I ACC, #I
--
ACC R ACC. ACC @P ACC. ACC WR I. ACC @P I. ACC ACC I.
ORL
R, ACC @P, ACC WR, #I @P, #I ACC, #I
--
ACC R ACC. ACC @P ACC. ACC WR I. ACC @P I. ACC ACC I.
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W53300/W53320
XRL
R, ACC @P, ACC WR, #I @P, #I ACC, #I
--
ACC R ACC. ACC @P ACC. ACC WR I. ACC @P I. ACC ACC I.
ANLR
R, ACC @P, ACC WR, #I @P, #I
--
ACC, R R ACC. ACC, @P @P ACC. ACC, WR WR I. ACC, @P @P I.
ORLR
R, ACC @P, ACC WR, #I @P, #I
--
ACC, R R ACC. ACC, @P @P ACC. ACC, WR WR I. ACC, @P @P I.
XRLR
R, ACC @P, ACC WR, #I @P, #I
--
ACC, R R ACC. ACC, @P @P ACC. ACC, WR WR I. ACC, @P @P I.
DEC
R @P ACC
CF
ACC, R R-1. ACC, @P @P-1. ACC ACC-1.
INC
R @P ACC
CF
ACC, R R+1. ACC, @P @P+1. ACC ACC+1.
SHLC
R @P ACC
CF
ACC.n, R.n R.n-1; ACC.0, R.0 0; CF R.3. ACC.n, @P.n @P.n-1; ACC.0, @P.0 0; CF @P.3. ACC.n ACC.n-1; ACC.0 0; CF ACC.3.
SHRC
R @P ACC
CF
ACC.n, R.n R.n+1; ACC.3, R.3 0; CF R.0. ACC.n, @P.n @P.n+1; ACC.3, @P.3 0; CF @P.0. ACC.n ACC.n+1; ACC.3 0; CF ACC.0.
RLC
R @P ACC
CF
ACC.n, R.n R.n-1; ACC.0, R.0 CF; CF R.3. ACC.n, @P.n @P.n-1; ACC.0, @P.0 CF; CF @P.3. ACC.n ACC.n-1; ACC.0 CF; CF ACC.3.
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Publication Release Date: March 1999 Revision A2
W53300/W53320
RRC
R @P ACC
CF
ACC.n, R.n R.n+1; ACC.3, R.3 CF; CF R.0. ACC.n, @P.n @P.n+1; ACC.3, @P.3 CF; CF @P.0. ACC.n ACC.n+1; ACC.3 CF; CF ACC.0.
SKBn (0 n 3) SKNBn (0 n 3) DSKZ
R @P ACC R @P ACC R @P ACC
------
IF R.n == 1, PC PC + 2. IF @P.n == 1, PC PC + 2. IF ACC.n == 1, PC PC + 2.
------
IF R.n == 0, PC PC + 2. IF @P.n == 0, PC PC + 2. IF ACC.n == 0, PC PC + 2.
--
ACC, R R-1; IF ACC == 0, PC PC+2. ACC, @P @P-1; IF ACC == 0, PC PC+2. ACC ACC-1; IF ACC == 0, PC PC+2.
DSKNZ
R @P ACC
--
ACC, R R-1; IF ACC != 0, PC PC+2. ACC, @P @P-1; IF ACC != 0, PC PC+2. ACC ACC-1; IF ACC != 0, PC PC+2.
JP JC JNC JZ JNZ JBn JNBn CALL RTN HOLD NOP SET CLR
L L L L L L L L
---------------------------------------------
PC L. IF CF == 1, PC L. IF CF == 0, PC L. IF ACC == 0, PC L. IF ACC != 0, PC L. IF ACC.n == 1, PC L. IF ACC.n == 0, PC L. STACK PC+1; PC L; STACK STACK+1. STACK STACK-1; PC STACK; ENTER THE HOLD MODE FOR POWER SAVING. NO OPERATION. IF I.n == 1, SR.n 1. IF I.n == 1, SR.n 0.
SR, #I SR, #I
---------
- 48 -
W53300/W53320
MOV
SR, ACC SRP, #I SR, #I
-----
SR ACC. SRP #I. SR #I.
MOV MOVA MOV
SR, RL RL, SR SR, RL RL, SR R, ACC ACC, R ACC, @LUPC ACC, @LUPC++
-----
SR RL. RL SR. ACC, SR RL. ACC, RL SR. R ACC. ACC R. ACC @LUPC. ACC @LUPC; LUPC LUPC+1.
-----
-----
MOV MOV MOV
R, #I @P, #I WR, R R, WR R, @P @P, R @RP1, @RP0 @RP0, @RP1
-----
R I. @P I. WR R. R WR. R @P. @P R. @RP1 @RP0. @RP0 @RP1.
-----
-----
MOV
R, @P++ @P++, R @RP1++, @RP0++ @RP0++, @RP1++
-----
R @P; P P+1. @P R; P P+1. @RP1 @RP0; RP0 RP0+1; RP1 RP1+1. @RP0 @RP1; RP0 RP0+1; RP1 RP1+1.
MOV
R, @LUPC @P, @LUPC R, @LUPC++ @P++, @LPUC++
-----
R @LUPC. @P @LUPC. R @LUPC; LUPC LUPC+1. @P @LUPC; LUPC LUPC+1; P P+1.
MOVA MOVA
R, #I @P, #I WR, R R, WR
-----
ACC, R I. ACC, @P I. ACC, WR R. ACC, R WR.
-----
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Publication Release Date: March 1999 Revision A2
W53300/W53320
MOVA
R, @P @P, R @RP1, @RP0 @RP0, @RP1
-----
ACC, R @P. ACC, @P R. ACC, @RP1 @RP0. ACC, @RP0 @RP1.
MOVA
R, @P++ @P++, R @RP1++, @RP0++ @RP0++, @RP1++
-----
ACC, R @P; P P+1. ACC, @P R; P P+1. ACC, @RP1 @RP0; RP0 RP0+1; RP1 RP1+1. ACC, @RP0 @RP1; RP0 RP0+1; RP1 RP1+1.
MOVA
R, @LUPC @P, @LUPC R, @LUPC++ @P++, LPUC++
-----
ACC, R @LUPC. ACC, @P @LUPC. ACC, R @LUPC; LUPC LUPC+1. ACC, @P @LUPC; LUPC LUPC+1; P P+1.
INC
RP0 RP1 LUPC
-----
RP0 RP0+1. RP1 RP1+1. LUPC LUPC+1.
CLR CLR EN DIS LCDON LCDOFF LD
DIV WDT INT INT
-------------------------
FLAG1.2 (DIVR bit) 0. FLAG1.1 (WDTR bit) 0. MR2.0 (INTEN bit) 1. MR2.0 (INTEN bit) 0. MR0.1 (LCDEN bit) 1. MR0.1 (LCDEN bit) 0. MOV LUP3,#i3 MOV LUP2,#i2 MOV LUP1,#i1 MOV LUP0,#i0
LUP
#i3i2i1i 0
LD
RP0
#i2i1i0
MOV RP0H,#i2 MOV RP0M,#i1 MOV RP0L,#i0
LD
RP1
#i2i1i0
MOV RP1H,#i2 MOV RP1M,#i1 MOV RP1L,#i0
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W53300/W53320
*Replacement table for instruction set Item WR R RL SR Replacement WR00, WR01, ...., WR0F, WR10, WR11, ...., WR3F RAM000, RAM001, ...., RAM00F, RAM010, ...., RAM37F RAM000, ...., RAM1FE, RAM1FF TM0H, TM0L, TM1H, TM1L, TMC1H, TMC1L, EVFH, EVFL, HEFH, HEFL, IEFH, IEFL, HCFH, HCFL, PEFH, PEFL, RP0H, RP0M, RP0L, RP1H, RP1M, RP1L, MLDH, MLDL, SPCH, SPCL, LCDM2, LCDM1, CF, FLAG1, FLAG0, MR2, MR1, MR0, SCR, LUP3, LUP2, LUP1, LUP0, LUC, WRPAGE, PSR1, PSR0, PM2, PM1, PM0, PORTA, PORTB, PORTC, PORTD, PORTE HEF, IEF RP0, RP1 8-bits or 4-bits immediate data
SRP P I
*Read/write property of each register Name TM0H TM1L EVFH HEFL HCFH PEFL RP0L RP1L SPCH CF MR3 MR0 LUP2 LUC PM1 PSR0 PORTC Type w w r,c r,w,s,c r r,w,s,c r,w r,w w r,s,c w r,w,s,c r,w r r,w,s,c r, clr-all r Name TM0L TMC1H EVFL IEFH HCFL RP0H RP1H MLDH SPCL FLAG1 MR2 SCR LUP1 WRPAGE PM0 PORTA PORTD Type w r r,c r,w,s,c r r,w r,w w w c s,c r,w,s,c r,w r,w r,w,s,c r, w r Name TM1H TMC1L HEFH IEFL PEFH RP0M RP1M MLDL LCDM1 FLAG0 MR1 LUP3 LUP0 PM2 PSR1 PORTB PORTE Type w r r,w,s,c r,w,s,c r,w,s,c r,w r,w w w r,w,s,c w r,w r,w r,w,s,c r, clr-all r,w w
w can use "MOV SR, R " instruction.. r can use "MOV R, SR " instruction c can use " CLR SR ' instruction. s can use " SET SR " instruction
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Publication Release Date: March 1999 Revision A2
W53300/W53320
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792697 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2730 Orchard Parkway, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
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